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From the Editor
Autumn in Germany
Whoever thinks that New England corners the market on fall foliage and festive occasions has never visited Stuttgart in October, nor driven from Stuttgart to Frankfurt on a clear autumn day. Last week, I was fortunate enough to do both last week all under the guise of attending SEMICON Europa, Oct 7-9, followed by a visit to Umicore for a tour of their electronic packaging materials manufacturing facility in Hanau. While most of the trip was work-oriented, I still made time to sample some of the local culture. My colleagues and I found it in abundance at the Cannstatter Volksfest, Stuttgart’s answer to Oktoberfest, as well as some local restaurants featuring the traditional Swabian fare of the region.
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FEATURES
Executive Panel Addresses Options in WLP
By Françoise von Trapp, managing editor
While last week’s executive panel during SEMICON Europa’s Advanced Packaging Conference was intended to focus on WLP and the supply chain, the panelist position statements and ensuing discussion skirted that particular issue almost entirely, and instead focused on which package designs themselves were more likely to take the lead. Panelists included Eef Bagerman from NXP Semiconductor; Hironori Tanaka, from Ibiden Co; Andreas Dill, from Oerlikon Balzers; Bernd Appelt, from ASE, Robert Darveaux representing Amkor, Kauppi Kujala from Nokia; and Paul Collander, of Poltronic and IMAPS Europe. The tone for discussion was set by Kujala’s presentation just prior to the panel, in which he addressed the three “hot” 3D options: embedded actives, 3D-IC, and fan-out wafer level packages (F-O WLP). Rolf Aschennbrenner, of Fraunhofer IZM, attended the panel discussion and offered his analysis of the event.
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Cooling 3D Packages with Thin-Film Thermoelectrics
By Paul A. Magill, Ph.D., Nextreme Thermal Solutions, Inc.
Electrical latency issues are set to become the limiting factor in obtaining higher processor speeds as the line sizes of the devices themselves continue to shrink. The electronics industry is moving to 3D packaging structures which will shorten the electrical path length, thereby allowing for higher transmission speeds. Of course, as this clears the way for faster processors, it also means that thermal management solutions for these 3D structures will also need to be developed. Cooling solutions will likely need to be integrated in a seamless manner into the existing packaging infrastructure.
Designing and Evaluating a TIM for Flip Chip Packages
By Vadim Gektin and Margaret Stern, Sun Microsystems; and Lyndon Larson, Dorab Bhagwagar, and Jesus Marin, Dow Corning Corporation and Kazumi Nakayoshi , Dow Corning Toray Co., Ltd.
As power levels and heat generation increase in high-performance CPUs and other semiconductor devices, the thermal performance of commonly used packaging components is becoming a limiting factor. Many such devices are mounted in flip chip packages, in which the die is underfilled on the active side and in direct contact with a thermal interface material (TIM), with a metal or ceramic lid attached on the opposite side. The lid serves as physical protection for the die as well as heat spreader and package stiffener, while the TIM helps to dissipate excess heat. With power levels steadily rising in new and emerging device designs, manufacturers are seeking improved thermal properties to ensure performance and reliability. A silver-filled silicone material specifically for TIM 1 applications (the die/lid interface) was designed to meet this challenge.
C4NP Process Update
Proven for High-volume 300mm Manufacturing
By Emmet Hughlett, SUSS MicroTec, Inc.
In July 2007, IBM announced the qualification of C4NP for 200µm pitch lead-free solder bumping for shipped product. Since then, IBM has qualified 150µm pitch C4NP lead-free bumped wafers on a fully populated high-volume production line. SUSS MicroTec is now completing build of additional C4NP equipment to meet ramping demand for lead-free bumping at IBM’s Hopewell Junction bumping facility. The next transition underway is micro-bumping for 3D applications. SUSS MicroTec, IBM, and select customers are into the second year of process development for micro-bumped wafer, defined as wafers with interconnect pitch at or below 50—m.
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The Riley Report
PS-PoP Packaging Pops Up
By George A. Riley, Ph.D.
Two weeks after I turned in my October Advanced Packaging round-up article on 3D stacking, a major packaging house, STATS ChipPAC, announced pre-stacked package-on-package (PS-PoP) its new approach to limit package warping during stacked PoP assembly. The usual supply chain for stacking one package on another is for the packaging company to assemble and test the matched upper and lower packages containing, for example, logic and memory die. These are then shipped separately to a surface mount provider who stacks and joins the two packages during board assembly.
Recent Headlines
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PRODUCTS
SEMICON Europa Product Showcase
Automatic Wafer Inspection
Viscom AG
Viscom AG has broadened its platform into the semiconductor market with the introduction of the MX20000IR fully automatic wafer inspection system. The application scope of the system includes MEMS, wafer bonds, flip chip and photovoltaics. Wafers can be composed of various materials including silicon, gallium arsenide, aluminum oxide or III-IV composites, and others. The tool can accommodate 150, 200 and 300mm wafers, robot-loaded either from cassette (150 and 200mm) or FOUP(300mm). Wafer identification and pre-alignment are done parallel to inspection, making the system suited to medium and large lot size inspection.
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Advanced Materials CVD and ALD Tool
Altatech
The AltaCVD chemical vapor deposition (CVD) and atomic layer deposition (ALD) tool from Altatech combines a unique vaporizer technology, chamber design, and gas/liquid panel integration. The combination of a proprietary reactor design and precursor introduction path with a pulsed liquid injection and vaporization is said to enable nanoscale control of thickness, uniformity, composition, and stoichiometry in complex materials. These depositions are reportedly unavailable today with existing techniques. is suited for plasma-enhanced MOCVD and ALD processes of a range of materials used in logic and memory devices, microsystems, and 3D integration including TSV metallization processes.
Nanoimprint Toolkit for Mask Aligners
SUSS MicroTec
SUSS MicroTec now offers a nanoimprint toolkit that reportedly enhances the capabilities of its manual mask aligners by enabling them to pattern large areas with repeatable sub-50 nm printing capability. The technology, substrate conformal imprint lithography (SCIL)was developed by Philips Research, (Eindhoven/The Netherlands) and transferred to SUSS MicroTec in a technology license agreement.
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Next-generation Contacting Sockets
Multitest, GmbH
The Multitest NanoKelvin socket was developed to meet the requirements of small pad QFN devices. It integrates the benefits of Kelvin technology with plunge-to-board capabilities. Proprietary Dura/Tecta coating combined with high contact force of 0.5 Newton at 0.4mm lead pitch and minimum scrub reportedly ensures electrical repeatability. The coating is said to guarantee socket lifespan of more that 1M Insertions. The socket uses contact spring blocks that allow for the exchange of contacted springs without the need for special tools or additional alignment.
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