Solid State Technology's WaferNEWS - www.wafernews.com
October 24, 2005
Welcome to WaferNEWS, the semiconductor manufacturing industry's weekly briefing of key business and technology trends, from the editors of Solid State Technology.
:: UP FRONT FEATURES :: IMEC, Infineon tout nitride-based flash memory
European R&D consortium IMEC and chipmaker Infineon Technologies AG say they have developed a new profiling technique for extracting charge profiles in nitride-based nonvolatile flash memory (NVM) and avoiding reliability problems. Nitride-based NVM is seen to be potentially more scalable than the conventional floating gate approach used in current flash memories.
Process simplicity and highly-localized charge-trapping mechanism in nanoscale material defects have drawn interest in nitride-based NVM. However, the technology requires hot holes for erasing, which causes accumulation of residual charges during write/erase cycles, and results in reliability problems including a "window walkout effect" (i.e., unstable threshold voltage) and degradation of retention after cycling.
IMEC and Infineon say they've developed a new profiling technique that allows for independent extraction of both electron and hole distributions, optimizing write and erase voltages and resulting in 100% matching of carrier profiles -- after one write/erase cycle, the "window walkout effect" disappears completely, and retention after cycling remains identical to retention of a fresh device. The technique also offers a smaller periphery (very may be skipped, and erase voltage is lower), and further channel length scaling is possible through sharper distributions.
:: TECH TALK :: IC Interconnect qualifies alternative wire bonding process
IC Interconnect, Colorado Springs, CO, has qualified a nickel/gold pad resurfacing process for high-temperature wire bond applications, targeting use in automotive and avionics devices. The process uses a 0.1-micron gold layer vs. traditional 1-micon layers, and offers a maskless alternative to avoid Cu corrosion than aluminum plating, which involves thin-film sputter, photolithography, and metal etch processes. The company also says its Ni/Au process eliminates Kirkendall voiding present in Al/Au interfaces at thermal exposures of 200 degrees Celsius.
:: Toppan develops 40nm-friendly mold method
Toppan Printing Co. has developed a method that cuts the time to fabricate molds for nanoimprinting 40nm semiconductor devices by 90%, and has demonstrated the process on a 200mm wafer. The method incorporates improved etch and metal-plating steps, and a new procedure to leverage the e-beam drawing devices used for mass production, a method less precise than prototype instruments but much faster, according to the Nikkei Business Daily.
:: INDUSTRY NEWS :: Analog shuttering CA fabs, moving work to MA, Ireland
Analog Devices Inc., Norwood, MA, is consolidating wafer fabrication operations in Sunnyvale and Santa Clara, CA, to its larger facilities in MA and Ireland, where the company works on more advanced process technologies.
:: IMEC embarks on R&D for 45nm RF-CMOS, neuroelectronic systems
European R&D consortium IMEC has added an RF-CMOS arm to its industrial affiliation program for researching sub-45nm CMOS technologies, expanding its efforts from an earlier 90nm program. IMEC also is partnering with the Flanders Interuniversity Institute of Biotechnology and the Katholieke Universiteit Leuven to set up an R&D research lab to develop neuroelectronic hybrid systems.
:: Flash provider SanDisk buys 3DIC firm Matrix
Flash memory card provider SanDisk Corp. has agreed to acquire Matrix Semiconductor Inc., a developer of 3D IC technology, for $250 million in cash and stock. With the deal, Matrix widens resources to manufacture and sell its 3D one-time programmable technology, which allows for multiple layers of memory within a chip. SanDisk sees use for Matrix's 3D IC technology as playing "an important role in content distribution," including SanDisk's new thumbnail-sized Gruvi memory cards offering preloaded music and other digital media content.
:: Samsung, Apple scuttle joint memory fab plans
Apple Computer has abandoned a proposed plan to build a $3.8 billion NAND flash memory fab with Samsung due to potential scrutiny by the South Korean Fair Trade Commission, which already is eyeing an investigation into Samsung for an alleged sweetheart deal to supply memory chips to the maker of the wildly popular iPod music players, according to Korean media reports. Apple reportedly is now in negotiations with another memory chipmaker.
:: IBM to make ZF Micro's x86 chips
IBM has signed a multiyear deal to be the foundry partner for ZF Micro Solutions' x86 chip designs, following a three-year legal battle to shop the design after National Semiconductor decided to cease production for the design. ZF's x86 FailSafe PC-on-a-chip will be produced at IBM's Burlington, VT facility, with sampling to begin in late 4Q05 and ramping to volume production in 1Q06. The two companies also indicated the relationship may be extended to include additional and even new products developed in conjunction with IBM's engineering and technology services division.
:: TSMC joins IMEC's sub-45nm party
Taiwan Semiconductor Manufacturing Co. (TSMC) has become the eighth core partner of IMEC's sub-45nm CMOS research program to push chip manufacturing technologies and processes down to the 32nm node and beyond. Efforts of the program now focus on lithography, frontend-of-line, advanced interconnects, cleaning and contamination control, and emerging devices.
:: SPANNING THE GLOBE :: CHINA
Anhui Province is putting the finishing touches on an 8-acre IC park in the southern region's capital of Hefei, with completion of surrounding infrastructure for water, power, and transportation access, according to the China Business Daily News. The total site is expected to require overall investment of roughly $500 million, including an IC design company for chips used in color TVS and cell phones, as well as a production line and a large packaging plant.
:: JAPAN
Silicon wafer supplier SUMCO, the JV between Mitsubishi materials Corp. and Sumitomo Metal Industries Ltd., plans to speed up its 300mm capacity expansion to 600,000 wafers/month (doubling today's levels) by the start of 2008, about six months earlier than originally planned, and wants to add an extra 100,000 wafers/month capacity by April 2009, according to the Nikkei English News. Total investments in the added capacity, at the company's facility in Imari, Saga Prefecture, will be about 130 billion yen (US$1.13 billion) from the current fiscal year.
:: JAPAN
Matsushita Electric Industrial Co. said it will begin shipments this month of its 65nm system chips used in digital consumer applications, sooner than its original year-end schedule, according to Dow Jones and Japanese newswires. The chips are being made at the company's 130 billion (US$1.13 billion) 3000mm facility in Uuzo, Toyama Prefecture, with initial output of 4300 wafers/month, ramping to 6500 wafers/month by 2007-2008. Matsushita is also mulling additional investments of 100 billion yen ($866.8 million) in 2008-2009 to double output to 12,000 wafers/month by 2010. The company plans chip-related capital expenditures of 86 billion yen ($745.4 million) in its current fiscal year though March 2006, a 6% increase from a year ago.
:: RUSSIA
A former employee of Toshiba's Discrete Semiconductor Technology subsidiary has been accused of leaking company secrets to a Russian trade official, according to newswire reports. The man allegedly received 1 million yen (about $US 8700) in exchange for information regarding insulated-gate bipolar transistors, which can potentially be used in military applications such as submarine radar or missile guidance systems.
:: SINGAPORE
Chartered Semiconductor posted revenues of $290.1 million in 3Q05, up 49.5% sequentially and 12.8% year-on-year, and a net loss of $34.5 million vs. a $67.1 million loss in 2Q05 and a $16.2 million profit in 3Q04. Sales of products utilizing 130-90nm process technologies rose to 41% of sales, largely due to the opening and initial ramp of Chartered's 300mm/90nm Fab 7, which opened in June and has ramped to 51,300 wafers/month (200mm equivalent). Total capacity rose 16% to 401,400 wafers/month, while overall fab utilization rates increased from 65% to 74%. Chartered projects revenues to jump 22%-25% in 4Q05 to $355-$363 million -- about 46% of that from 130-90nm process technologies, and forecasts a $5-$15 million profit.
:: SOUTH KOREA
Hynix Semiconductor Inc. posted a net income of roughly $490 million in 3Q05 on revenues of $1.43 billion, compared with profits of $228 million in 2Q05 on sales of $1.18 billion. Profits were down 3.5% from the same quarter a year ago, while sales were down 3.5%. The 115% increase in profits and 21% sales jump were attributed to DRAM price increases during a seasonal demand pickup, and strong demand for NAND flash memory -- Hynix's bit growth rose 3% quarter-on-quarter for DRAM and 80% for NAND flash.
:: TAIWAN
DRAM supplier ProMOS Technologies has secured a $388.7 million loan from a consortium of banks to help finance construction of its second 300mm fab, located in the Central Taiwan Science Park, according to the Taiwan Economic News. Fab 3 is expected to ramp to 30,000 wafers/month utilizing 90nm process technologies by 3Q06, and upgraded to 70nm and output of 40,000 wafers/month by 4Q06. ProMOS plans to break ground on a third 300mm/60nm fab in mid-2006 in the park, to open in late 2007 with 40,000 wafers/month capacity, and plans to convert a 200mm fab to 300mm operation in 200 as well.
:: WaferNEWS FAB 50
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:: TESTING TESTING :: Backend sector leads return to growth in September chip tool demand
Both sides of the semiconductor equipment and IC demand coin are showing improvement as the industry ramps up to meet projected holiday demand, according to data from VLSI Research Inc.
:: STATS ChipPAC shrinks packaging sizes below 0.5mm
Singapore-based backend services provider STATS ChipPAC has introduced a new line of ultrathin, ball-grid array and land-grid array packages with profile heights of <0.50mm to accommodate substrate-based molded packages instead of bare die. The packages utilize a 0.13-micron two-metal-layer laminate substrate, wafer thinning down to 75 microns, and new molding technology to minimize warpage. The XFBGA and XFLGA packages are available in single or multiple-die arrays utilizing lead-free material sets, with or without eutectic or lead-free solder balls.
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