Big push coming on two routes to 3D
by Bob Haavind, Editorial Director, Solid State Technology
3D chip packaging with through-silicon vias will sweep across the industry over the next 3-5 years, enabling very compact packaging offering much better performance, and many chipmakers see 3D as an interim...   More >>

Keynotes tap into promises, challenges of solar
by Phil LoPiccolo, Editor-in-Chief, Solid State Technology
A pair of Wednesday keynotes at SEMICON West described opportunities for semiconductor suppliers in the solar energy market, but cautioned that there are fundamentally different manufacturing requirements...   More >>

NEWS HEADLINES FROM SEMICON WEST:

- SEMI names 2007 standards award recipients
-   More >>

Lam tips details about C3 linear cleaner for ultra-thin films
by Ed Korczynski, senior technical editor, Solid State Technology
Lam Research Corp. has finally revealed some of the details of its new linear atmospheric cleaner, which targets high-selectivity cleans with short contact times—on the order of ~1 seconds. "We think...   More >>

To FUSI or not FUSI? That's the question
by Debra Vogler, senior technical editor
SEMATECH's Raj Jammy talks about the group's work with gate first/high-k metal-inserted poly stack (MIPS) electrode approach, instead of FUSI or replacement gates, in a pre-show interview with WaferNEWS.   More >>

AMAT: The transistor is cool again!
by M. David Levenson, Editor-In-Chief, Microlithography World
The main topics for discussion at Applied Materials' big press event this week were about high-k/metal gate processes (HK+MG) and double patterning lithography, though much of the talks concentrated...   More >>

Materials establishing firm foothold in advanced packaging
by Françoise von Trapp, managing editor, Advanced Packaging
At Wednesday's Packaging Materials Trends TechXPOT, industry experts shared insights and developments in packaging materials and applications, and how innovations will help device packaging address...   More >>

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