Enabling high-volume fine-pitch Cu wire bonding
As gold becomes more expensive, copper wire bonding becomes more appealing for chip packaging, with several bonding technologies (reverse, fine-pitch, looping, second bonds) ramping on roadmaps. In an interview with SST's Debra Vogler at a recent iMAPS meeting, Bob Chylak from Kulicke & Soffa talks about the heightened activities to close the knowledge gap with respect to using copper.
3D IC is only solution for scaling "up," says MonolithIC 3D exec
Zvi Or-Bach, MonolithIC 3D, describes the TSV-beating monolithic IC fab process, and argues for scaling "up" rather than down. Or-Bach compares the costs of further semiconductor scaling to advanced packaging.
Remembering interconnect giants
Dimitry Grabbe, Jack Baide, George Messner -- three honored researchers whose accomplishments and leadership shaped our world of microelectronic interconnect technology, writes Dr. Phil Garrou.
News & Analysis
IITC preview: IBM BEOL interconnect tech for <22nm
Shyng-Tsong Chen, lead integrator for back-end integration at IBM's Albany Nanotechnology Center, tells SST's Debra Vogler about his upcoming presentation at IITC on "64nm pitch Cu dual-damascene interconnects using pitch-split double-exposure patterning scheme." This technology will be needed for BEOL interconnects beyond 22nm devices. - Beyond ball shear test: Stanford presenting microprobing stress data at IITC
Copper pillars taking over flip chip, some leadframe packaging
Following Intel's lead, many companies are moving to adopt copper pillar as the technology for their flip chip applications, as well as leadframe packages. TechSearch's E. Jan Vardaman says the move to Cu pillar is reminiscent of the transition from the evaporated bump to the plated bump. - Flip chip still growing, thanks to Cu pillars, 28nm
AMAT, Singapore IME create WLP center
The planned "Center of Excellence in Advanced Packaging" run by Applied Materials and the Institute of Microelectronics, with a full line of wafer level packaging processing equipment, will conduct research in semiconductor hardware, process, and device structures. - CEA-Leti deploys EVG's litho, packaging tools for 300mm line
STATS ChipPAC expands TSV service with mid-end flow
STATS ChipPAC is expanding its 300mm through silicon via (TSV) offering with the addition of mid-end manufacturing capabilities.
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