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:: July 7, 2005 |
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:: SST Review
: Lithography/DFM
In this edition of SST Review, the following collection of articles from Solid State Technology, Microlithography World, and WaferNews focuses on the challenges and solutions for 65nm and below photolithography processes, including the rapidly evolving segment of design for manufacturing (DFM). As device feature sizes continue to shrink far below exposure wavelengths, the importance of DFM, resolution enhancement techniques (RET), and lithography simulation software grows. New software tools are also needed to optimize optical proximity correction (OPC) for immersion ArF scanners, which are expected to be deployed in production fabs during the next couple of years. |
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:: Why simulation could push designers to start using DFM Narrowing process windows, emerging tools for statistical analysis of design, and model-based simulations of yield results may soon push designers to actually design for manufacturability, argued experts at SEMI's recent Strategic Business Forum. Dr. Paula Doe, Contributing Editor WaferNews, May 23, 2005 :: Click for Full Story :: 
:: AAPSM space-imbalance reduction for 65nm lithographyRigorous vector simulations show how to minimize the intensity imbalance of spaces with opposite phases for 65nm-node alternating-aperture phase-shifting masks. Strategies such as undercut, bias, and a combination of undercut, bias, and a transparent etch-stop layer are compared. Alternate phase targets and modified sidewall profiles were also simulated. Tejas Jhaveri, Rand Cottle, Yuan Zhang, Christopher J. Progler, Photronics Inc. Microlithography World, May 2005 :: Click for Full Story :: :: New priorities reshape DFM landscape Listening to industry experts at SPIE's recent International Symposium on Microlithography, one theme was clear: The design-for-manufacturing (DFM) sector is becoming a hotbed of diversity, drawing interest from all points of the semiconductor manufacturing chain. The real question, however, appears to be how DFM solutions will be integrated into design and process flows, and just how much of an advantage IDMs will have on their foundry competitors. Debra Vogler, Senior Technical Editor WaferNews, April 11, 2005 :: Click for Full Story :: :: Microlithography process development with lithography simulation Microlithography simulation has become essential in the last decade, driven by the increasingly challenging lithography requirements of subwavelength imaging technologies. John Lewellen, Peter Brooker, Bob Naber, Sigma-CAD; Uli Hofmann, Sigma-C Microlithography World, February 2005 :: Click for Full Story :: :: Perspectives: 'Design for manufacturing' spreads Solid State Technology asked design automation managers how DFM software is shifting the responsibilities for wafer yields. Mark Miller, Cadence Design Systems Inc.; Srinivas Raghvendra, Synopsys Inc. Solid State Technology, February 2005 :: Click for Full Story :: :: Model-based RET using interference maps, algorithms for random contacts at 65nm Wafer-exposure imaging conditions and interference maps are employed by a novel model-based approach for optimum placement of resolution enhancement features on subwavelength photomasks. Douglas J. Van Den Broeke, Kurt Wampler, Xuelong Shi, Robert Socha, Keith Gronlund, ASML MaskTools Solid State Technology, September 2004 :: Click for Full Story :: :: Modeling of immersion lithography for OPC Liquid immersion optics create challenges for the optical lithography models used inside OPC software. Advanced models show the improvement in DOF expected for NA<1 and can cope with the subtleties of polarization and other effects expected for NA>1. Konstantinos Adam, Mentor Graphics Corp. Microlithography World, August 2004 :: Click for Full Story :: :: Optimized illumination settings extend ArF lithography to 65nm Resolution-enhancement techniques such as darkfield alternating phase-shift masks, double dipole exposures, and chromeless lithography will be needed to apply ArF tools to the 65nm node while device makers wait for production-class high-NA immersion scanners to arrive around 2007. Shu-Hao Hsu, Shu-Ping Fang, I.H. Huang, Benjamin Szu-Min Lin, Kuei-Chun Hung, United Microelectronics Corp. Solid State Technology, August 2004 :: Click for Full Story :: :: Exploiting design regularity for optical RET lithography Semiconductor lithography is facing a critical crossroads. In the mid-1990s, minimum feature sizes began to drop below available exposure wavelengths and over the last several years this trend has continued. Michael Fritze, Brian Tyrell, MIT Lincoln Laboratory Solid State Technology, August 2004 :: Click for Full Story ::
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