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SST Global: Asia Pacific

   :: February 9, 2006    





:: SST Global: Asia Pacific

Welcome to the February 2006 edition of SST Global: Asia-Pacific, a monthly e-newsletter from the editors of Solid State Technology and WaferNews. This month's issue is a comprehensive but concise collection of articles that can help our readers in the Asia-Pacific region stay on top of the latest technology developments and industry news about semiconductor manufacturing.



:: SEMICON Japan News roundup: Lots of action in materials and inspection sectors
Big players introduced tools for 45nm production at SEMICON Japan, but much of the activity was in improved materials that could at least be hyped as nanotechnology, and of course in more new types of metrology tools, with wafer-edge inspection a particularly hot niche for new product introductions. Paula Doe, Contributing Editor
WaferNews,
January 3, 2006
::  Click for Full Story  ::

:: Outlook 2006: Analysts maintain caution, optimism for semiconductor market growth
Analysts surveyed generally see steadily improving growth for the semiconductor market for the next three years — and more muted cycles than the wild days of the past. Projections for chip sales in 2006 cluster in the mid single digits, although the optimists see as much as 17%-20% growth, thanks to a healthy world economy and plenty of hot consumer products. James Montgomery, News Editor
WaferNews
, January 3, 2006
::  Click for Full Story  ::

:: SEMICON Japan: Suppliers tout immersion and EUV progress
With 65nm production ramping, the focus at SEMICON Japan turned to cutting-edge technology for 45nm production and 32nm development, leaving lithography suppliers in the unenviable position of midwifing two new exposure technologies into production at once. Masataka Tsubo, Contributing Editor, Japan
WaferNews,
January 3, 2006
::  Click for Full Story  ::

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:: Three Japanese chipmakers mulling scaled-down joint foundry
Hitachi, Toshiba, and Renesas have agreed to move forward with planning a considerably scaled-down version of the long-rumored joint Japanese foundry. Paula Doe, Contributing Editor
WaferNews,
January 3, 2006
::  Click for Full Story  ::

:: Integrating MEMS devices using low-temperature wafer bonding
The scaling and integration of MEMS devices across application platforms often leads to difficult problems that can be addressed by limiting thermal processing temperatures. S. Farrens, P. Lindner, V. Dragoi, G. Mittendorfer, EV Group.
Solid State Technology
, February 2006
::  Click for Full Story  ::

:: IEDM: Industry reports progress toward metal gates, high-k dielectrics
Several approaches to metal gate processing and integration with high-k dielectrics for the 45nm node and beyond were reported at the recent International Electron Devices Meeting (IEDM) in Washington, DC. Bob Haavind, Editorial Director
WaferNews,
January 9, 2006
::  Click for Full Story  ::

:: Accuracy, speed, new physical phenomena: The future of litho simulation
Just as lithography technology moves at a harried pace toward finer features, simulation technology must move just as fast to stay with, or ahead of, the needs of lithography development. Chris A. Mack
Solid State Technology,
February 2006
::  Click for Full Story  ::

:: Advanced process control extends ECMP process consistency
Electro-chemical mechanical planarization (ECMP) provides greater control capabilities compared to CMP processes, and a multizone cathode allows for precise control over within-wafer uniformities. Antoine Manens, Paul Miller, Eashwer Kollata, Alain Duboust, Applied Materials Inc.
Solid State Technology,
February 2006
::  Click for Full Story  ::

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