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:: May 3, 2007 |
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:: SST Review
: Interconnect
In this edition of SST Review, we present articles that focus on the leading edge of technology developments in IC interconnects. Below you will find selected articles from Solid State Technology and WaferNews covering the newest technologies used to connect circuit elements on-chip and between chips, with an emphasis upon 3D chip structures to increase performance and density, and a focus upon new materials such as carbon nanotubes. |
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:: Copper-nail TSV technology for 3D-stacked IC integrationMaking reliable systems through direct interconnection between dice requires proper integration of via-processing technology as well as thinning and stacking technologies. All technology variations influence stack performance and cost, and the seemingly most obvious choice for any one technology does not always lead to the best overall system integration. Koen Snoeckx, Eric Beyne, Bart Swinnen, IMEC Solid State Technology, May 2007 :: Click for Full Story :: 
:: IITC Preview: CNT interconnects target 32nmAmong the noteworthy developments to be discussed at this year's International Interconnect Technology Conference are advances in fabricating carbon nanotubes (CNTs) for use in via applications. A paper from MIRAI-Selete describes a novel process for forming CNT vias, and reports CNT interconnect performance characteristics that meet 32nm mode requirements and beyond. In related work, a team from Rensselaer Polytechnic Institute will present a technique to increase the density of post-growth CNT bundles to improve conductivity, potentially beyond that of copper. Phil LoPiccolo, Editor-in-Chief WaferNews, April 23, 2007 :: Click for Full Story :: :: Electron Devices Meeting goes 3D, low power Highlights of the recent International Electron Devices Meeting in San Francisco included work on strained silicon to increase speed at lower voltage to cut operating power, novel materials for metal gates and high-k dielectrics to limit leakage power loss, and improvements in low-k dielectrics in interconnects to boost speed at lower power. Bob Haavind, Editorial Director Solid State Technology, February 2007 :: Click for Full Story :: :: Integrating photonics: Hitachi, Oki put LEDs on silicon Hitachi Ltd.’s central research laboratory reports making a light-emitting diode (LED) from ultrathin silicon thin film with conventional CMOS technology, a step toward potentially putting high-speed optical connections on conventional low-cost silicon devices, without the issues of integrating compound semiconductor materials with standard silicon, reports SST partner Nikkei Microdevices. Paula Doe, Contributing Technical Editor Solid State Technology, January 2007 :: Click for Full Story :: :: Wafer-level packaging boosts yields of chip-on-board image sensors Chip-on-board (COB) is the most dominant assembly process used to build over a million camera modules each day of the year. However, as the market moves to cameras with ever-higher pixel counts, COB assembly becomes increasingly difficult due to contamination of the optical sensor. An effective way to prevent contamination is to place a cover over the image sensor at the wafer level, and leaving the bond pads exposed allows for full compatibility with the COB assembly process. Giles Humpston, Tessera, Yehudit Dagan, Tessera Israel Ltd. Solid State Technology, November 2006 :: Click for Full Story :: :: Fujitsu reports progress towards carbon nanotube interconnects for 32nm Fujitsu has demonstrated selective growth of vertical bundles of carbon nanotubes in 40nm via holes uniformly across 300mm wafers at temperatures of ~450°C, with resistance as low as tungsten, edging closer to the target of matching the resistance of copper at CMOS-compatible growth temperatures of 400°C, reports SST partner Nikkei Microdevices. Paula Doe, Contributing Editor, and Yuji Awano, Fujitsu Laboratories Ltd., from SST partner Nikkei Microdevices Solid State Technology Online Exclusive Feature, November 2006 :: Click for Full Story :: :: Using ultrasonics to measure the strength of porous ULK dielectrics Picosecond ultrasonics tools can rapidly measure the mechanical strength of porous dielectrics with k values approaching 2, and can resolve within-wafer uniformity. The technique can be used to develop more robust deposition processes and to control those processes in high-volume production. LL. Chapelon, D. Neira, J. Torres, STMicrolectronics, F. Naudin, J. Clerico, Rudloph Technologies Solid State Technology, November 2006 :: Click for Full Story :: :: Alternatives to low-k nanoporous materials: dielectric air-gap integration Air gaps formed within multilevel on-chip interconnect structures are now under serious consideration as a means to lower the k value of intermetal dielectrics (IMD) for future manufacturing nodes. In fact, several integrated process flows can create air gaps, using established unit processes for deposition and etch. Preliminary analyses of these techniques indicate that air-gap structures can be formed with acceptable yield, structural integrity, and reliability. Romano Hoofman, Roel Daamen, Julien Michelon, Viet Nguyenhoang, Philips Research Solid State Technology, August 2006 :: Click for Full Story :: :: Combining seed layers enables the use of HAR copper interconnects The lower resistivity of copper vs. aluminum facilitates denser and faster ULSI devices with on-chip copper interconnects. However, the shrinking dimensions with each new technology generation rapidly increase the RC delays in-line resistance, signal loss, power dissipation, heating, and thermal stress of the copper interconnect. However, these shortcomings can be mitigated by using high-aspect ratio (HAR) copper interconnects. Uri Cohen, UC Consulting Solid State Technology, July 2006 :: Click for Full Story ::
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:: SUBSCRIPTION INFORMATION  For more stories from SST's website, connect to the homepage by clicking here: http://www.solid-state.com Editor: James Montgomery - jamesm@pennwell.com SST Review is delivered electronically on the first Thursday of each month at no charge. SST invites you to forward this newsletter to colleagues or associates who might be interested in our weekly news summaries. :: If you are a current subscriber, you can discontinue delivery of SST Review by clicking this UNSUBSCRIBE link: @{confirmunsubscribelink:sst-media.com}@ You can also reply to the original e-mail and type "Unsubscribe" in the subject line. Or, if you prefer, you can write to us at: PennWell Corporation c/o E-mail Unsubscribe 1421 South Sheridan Road Tulsa, OK 74112 :: If you do not subscribe to this newsletter and would like to receive it, please click this link: SUBSCRIBE |
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